Physical Design Technical Leader/Manager
- Singapore
- Permanent
- Full-time
- Leading the technical execution of logic synthesis and design optimization for AI-focused compute architectures, including TPUs, NPUs, and custom accelerators.
- Driving optimization of high-speed arithmetic structures such as MAC arrays, SIMD engines, and systolic arrays for AI workloads.
- Providing hands-on expertise in STA, constraint development, and clock tree synthesis (CTS) to meet timing goals across complex multi-clock domains and high-frequency data paths.
- Applying advanced low-power design techniques (e.g., clock/power gating, dynamic voltage scaling) to reduce energy consumption in AI chip designs.
- Defining memory hierarchy strategies (SRAM, DRAM interfaces, cache subsystems) to support AI performance and efficiency.
- Collaborating with DFT teams to support scan insertion, MBIST, and JTAG integration while ensuring clean handoff for physical implementation.
- Partnering closely with physical design teams to resolve congestion, meet timing, and provide physical-aware synthesis and design constraints tailored to AI architectures (e.g., NoCs, high-speed interconnects).
- Leading the formal verification and equivalence checking process to ensure functional accuracy between RTL and synthesized netlists.
- Acting as a technical mentor and go-to expert for synthesis, timing closure, and power optimization, providing guidance and technical reviews across engineering teams.
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- 8 years of hands-on experience in ASIC design, with a strong focus on synthesis, STA, and power optimization for complex SoCs or AI accelerators.
- Solid understanding of RTL-to-GDSII flows and hands-on experience with EDA tools such as Synopsys Design Compiler, Cadence Genus, PrimeTime, and Innovus.
- Expertise in managing multi-clock domain designs, advanced timing closure techniques, and low-power methodologies (e.g., UPF, DVFS).
- Familiarity with AI-specific architectures, including NoC design (mesh, torus, AXI), memory optimization (HBM, SRAM), and chiplet-based packaging (2.5D/3D integration).
- Proficiency in RTL coding (Verilog/SystemVerilog) and scripting (TCL, Python, Perl, Shell) for automation.
- Strong collaboration and problem-solving skills, with the ability to lead complex technical discussions and resolve design bottlenecks effectively.
- A culture that embraces authenticity, innovation, and diversity of thought.
- A startup environment that encourages openness, curiosity, and bold ideas.
- Opportunities to work on cutting-edge hardware for the digital asset and AI industries.
- High-impact contributions on strategic projects that shape the future of AI compute.
- Autonomy, personal accountability, and accelerated learning in a fast-moving environment.
- Attractive benefits and access to mentorship, technical training, and career development resources.