
Silicon Design Engineer
- Singapore
- Permanent
- Full-time
- Drive formal verification for the block and write formal properties and assertions to verify the design
- Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design
- Write tests, sequences, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the design
- Responsible for verification quality metrics like pass rates, code coverage and functional coverage
- Project level experience with design concepts and RTL implementation for same
- Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics
- Good understanding of computer organization/architecture
- Bachelors or Masters degree in computer engineering/Electrical Engineering