
Staff Physical Design Engineer
- Singapore
- Permanent
- Full-time
- Develop and implement plans to synthesize, implement Design-For-Test (DFT) and close timing on complex digital integrated circuits.
- Work with various design groups across different disciplines (Logic, Circuits, DFT & Layout) to meet timing closure, area, power, and performance requirements.
- Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.
- Analyze log and report files to ensure the tools are getting the required results and make adjustments to the scripts to get the required results within the scheduled milestones.
- Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule.
- Provide/propose new/enhance synthesis, DFT and STA flow and methodology to reduce the development TAT to meet product requirements.
- Proficient in IP level ASIC physical design including hierarchical implementation
- Proficient in using physical design RTL2GDS EDA tools and working in Linux and Windows environments
- Experienced with Verilog, System Verilog, C, and C++
- Automating workflows in a distributed compute environment.
- Good understanding and hands-on experience in timing constraints development
- Scripting language experience: Perl, TCL, Makefile, shell preferred.
- Exposure to leadership or mentorship is an asset
- Bachelors or Masters degree in Computer Engineering/Electrical Engineering