
Senior Engineer, Analog Layout
- Singapore
- Permanent
- Full-time
- Physical layout and verification of high speed I/O circuits, General Purpose I/Os, ESD structures with the latest process nodes using Cadence tools.
- Work closely with ESD leads to support worldwide Marvell in IP/SoC ESD/LUP DRC/ERC reviews (training will be provided).
- Work closely with CAD team to implement ESD/LUP rules for different process nodes.
- Help with releasing I/O IP libraries.
- Help implement project specific guidelines and conduct peer-to-peer layout quality checks.
- Contribute to overall team through tool testing, script development, flow documentation, training, etc.
- Keep abreast with technology, tool developments and bring new ideas to the team.
- Bachelor’s or Master's degree in Computer Science, Electrical Engineering or related fields and at least 3+ years of related professional experience.
- Good understanding of semiconductor and circuit design.
- Good understanding of analog mixed-signal layout best practices.
- Have high level proficiency/knowledge of Synopsys or CADENCE layout entry tools.
- FinFet layout experience is a plus.
- ESD / latch-up knowledge is a plus.
- Have high level proficiency in the interpretation of CALIBRE DRC, ERC, LVS, etc. reports.
- Scripting skills in PERL, TCL or SKILL are considered a plus, but not required.
- Independent with strong analytical skills, creative thinking and self-motivated.
- Excellent communication skills and able to work with cross-functional teams.
- Ability to thrive in a fast-paced, global environment.