Senior Staff/Staff Design Verification Engineer

Silicon Labs

Singapore
Permanent
Full-time

2 months ago

We are Silicon Labs. We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives.Meet the TeamThe IoT Digital team is a state-of-art IC design team focused on producing world-class Wireless MCU SoCs. The architecture specification, design, verification, and implementation of the Wireless MCU SoCs is the responsibility of the IoT Digital team. These SoCs include an embedded CPU system with analog and digital peripherals, advanced security, state-of-the-art power management, and best-in-class radios to support a wide range of wireless IoT applications and standards.As Senior Staff Verification Engineer, you will be working closely with the IC Design, System, and Architecture teams to develop and execute the verification plan for the next generation of IoT chips.ResponsibilitiesBlock and IP VerificationBlock-level verification to validate block performance and adherence to requirementsGenerate and execute verification plan based on specificationsArchitect and implement test benches using UVM-based constrained-random and formal methodsCoverage definition, implementation, and analysisFormal Verification of mixed-signal IP integration, including real-number modelingSoC Integration and VerificationDefine, test and debug use cases for the SoCVerify and debug low-power designFlows and MethodologyImprove flows and methodologies to streamline IP development and integration.Skills You Will Need
Minimum Qualifications:Min. 15 years of IC design experience for senior positions. Open to junior candidates with strong foundation.Industry experience developing test benches and verification components with SystemVerilog and UVM is requiredKnowledge of scripting/language (Python, PERL, shell, TCL)Design/Verification skills such as Software/Firmware coding (C), SystemVerilog Assertion and coverage analysis, Low-power implementation (UPF), Mixed Signal Real Number Modeling (RNM, Spice)Benefits & Perks:
You can look forward to the following benefits:Employee Stock Purchase Plan (ESPP)Insurance plans with Outpatient coverFlexible work policy#LI-Hybrid#LI-DK1We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

Silicon Labs

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